The present invention relates to a process for preparation of a SONOS flash memory device including an ultraviolet (UV) radiation blocking layer for reducing UV-induced charging of device in back-end-of-line (BEOL) processing.
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. One EEPROM device that utilizes the ONO structure is a silicon-oxide-nitride-oxide-silicon (SONOS) type cell. A second EEPROM device that utilizes the ONO structure is a floating gate FLASH memory device, in which the ONO structure is formed over the floating gate, typically a polysilicon floating gate.
In SONOS devices, during programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region. Because silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous silicon nitride layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a dual-bit EEPROM, which is available under the trademark MIRRORBIT(trademark) from Advanced Micro Devices, Inc., Sunnyvale, Calif. The MIRRORBIT(trademark) dual-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two bits to be programmed and read simultaneously. The two bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
A key concept associated with the SONOS flash memory device is that for the device to operate properly, both bits must be able to be written and read separately. If one of the bits is programmed, a reverse read on the programmed bit must sense a high Vt, i.e., a xe2x80x9c0xe2x80x9d, and a reverse read on the non-programmed bit must sense a low Vt, i.e., a xe2x80x9c1xe2x80x9d. Thus, a reverse read on the non-programmed bit, which is equivalent to a forward read on the programmed bit, must punch through the region of trapped charge in order to generate a high enough read current. If this does not happen, the non-programmed bit will not be able to be read as a xe2x80x9c1xe2x80x9d, i.e., a conductive bit.
One problem which has been encountered with SONOS flash memory devices including a dielectric charge storage layer is the buildup of charge in the charge storage layer, and subsequent increases in Vt, as a result of exposure to ultraviolet radiation during fabrication, and particularly in BEOL process steps, i.e., following formation of the flash memory cell. Processes which include high levels of UV radiation cause such charge buildup and concomitant increase in Vt. This increase in Vt would make all the bits appear to be high, i.e., xe2x80x9c0xe2x80x9d. In addition, if the charge buildup is sufficiently large, it cannot be easily erased by the available voltages. As a result, the SONOS device would be rendered useless as a charge storage device.
UV exposure is not a problem for floating gate flash devices which have a polysilicon or other conductive material for a charge storage element. In such devices, the floating gate may be purposely exposed to UV radiation, in order to neutralize any electronic charge which builds up on the floating gate memory cell during processing. For example, U.S. Pat. No. 6,350,651 uses UV radiation in this manner.
Such processing is not an option for SONOS flash memory devices, since the charge storage layer can be irreversibly damaged by exposure to UV radiation which builds up a large charge, and the charge cannot be neutralized by further exposure to UV radiation.
Therefore, a need exists for a method which will provide, and a device which includes provision for, protection of the charge storage layer in SONOS devices from exposure to UV radiation during BEOL processing. Accordingly, advances in such fabrication technology are needed to insure that charge buildup and increase in Vt in SONOS structures does not occur, particularly during BEOL processing.
The present invention, in one embodiment, relates to a SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material.
In one embodiment, the present invention relates to a SONOS flash memory device, including a SONOS flash memory cell; a UV-protective contact cap layer disposed over the SONOS flash memory cell, the UV-protective contact cap layer comprising a substantially UV-opaque material; and at least one additional UV-protective layer, the at least one additional UV-protective layer comprising at least a sub-layer of a UV-opaque material in which each UV-opaque material comprises one or more of silicon-rich silicon dioxide, silicon-rich silicon nitride, silicon-rich silicon carbide or silicon-rich SiCN, and in which the UV-protective layers protect the SONOS flash memory cell from damage resulting from UV exposure during BEOL processing in fabrication of the SONOS flash memory device.
In another embodiment, the present invention relates to a method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, wherein the UV-protective layer comprises a substantially UV-opaque material.
In one embodiment, the UV-protective layer protects the SONOS flash memory cell from damage resulting from UV exposure during BEOL processing in fabrication of the SONOS flash memory device.
Thus, the present invention, by providing a UV-protective layer, overcomes the problem of UV-induced charging of SONOS flash memory cells, particularly during BEOL processing. The present invention provides advantages such as (1) formation of a UV-protective layer which protects the device from BEOL UV radiation; (2) protection of the SONOS flash memory cell from UV-induced charging; (3) provision of a process modification which can be easily accommodated in presently employed fabrication processes; and (4) formation of one or more of a contact cap layer, interlevel dielectric layers, and a top oxide with this additional function in addition to standard dielectric functions. Thus, the present invention provides an advance in ONO fabrication technology, and insures proper charge isolation in ONO structures in SONOS flash memory devices, while at the same time providing distinct process and economic advantages. Although described in terms of, and particularly applicable to, SONOS flash memory devices, the present invention is broadly applicable to fabrication of any semiconductor device that includes a charge storage layer subject to unwanted UV charging.